In JP-A-2011-172336, temperatures of semiconductor devices are represented by duty cycles of PWM signals, and the PWM signals are serially outputted from a single output terminal. In such a structure, a receiver for receiving the PWM signals needs to distinguish the PWM signals from each other. Therefore, it is necessary to form an edge in the PWM signals by limiting a duty cycle of each PWM signal. For example, as shown in FIGS. 12A and 12B, when a duty command (i.e., analog signal input) indicates a duty cycle of 100%, a 100% duty cycle PWM signal is outputted accordingly. In this case, the boundary between the PWM signals becomes indefinite. In contrast, as shown in FIG. 12C, when the upper limit is set on the duty cycle of the PWM signal, the boundary between the PWM signals becomes definite.
To obtain the temperature over a wide range, accuracy with which the duty cycle is limited is important. In JP-A-2011-172336, the duty cycle is limited by using an analog circuit such as a comparator. Since a threshold voltage of the comparator and an amplitude of a carrier wave may vary, the accuracy may be low. For example, assuming that the accuracy is 10%, when both an upper limit and a lower limit are set on the duty cycle, variation of 10% may occur in each of the upper limit and the lower limit. Therefore, it is necessary to limit the maximum duty cycle to 80%.
In US 2004/0150379 corresponding to JP-A-2004-229451, an upper limit is set on a duty cycle of a PWM signal used for a switching regulator. The duty cycle is limited by using a current mirror circuit. Thus, even when a manufacturing variation or an ambient temperature change occurs, the variation or change is cancelled so that the duty cycle can be limited with high accuracy.
However, when the duty cycle is limited close to 0% or 100% by using a current mirror circuit, the current mirror circuit needs to have a small or large mirror ratio. As a result, the accuracy with which the duty cycle is limited may become low.